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Transactions between PCIe endpoints bypass the root complex. This means that any device downstream of an IOMMU is not aware and is not separated from other devices within this group. Since the host OS creates virtual memory spaces for each guest OS, it is set up to address and treat each group of devices “underneath” an IOMMU (an IOMMU group) as the smallest set of devices that can be isolated from other groups. This is called direct-memory access (DMA).Įven though these IOMMUs can talk to each other through DMA directly, not every device has its own management unit that can perform the translation from physical memory space to the device itself.
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This physical hardware is especially important for high speed communication devices, as features such as data transfers can be set-up by the CPU, and then offloaded to these MMUs to handle on their own. These input / output (IO) devices will then have their own MMU, or an IOMMU, similar to how main memory does. Most devices connected to the CPU are actually mapped into memory addresses similar to RAM. RAM is not the only “physical” memory address, however. This MMU translates the virtual addresses of the user program / virtual machine in the CPU into physical addresses that are physically located in RAM. The kernel of the host OS works with this MMU to create virtual memory spaces for all user programs (and even guest OS). This means that its kernel manages the CPU and the CPU interfaces with memory through a memory management unit (MMU). At a basic level, though, the host OS is running on all of the physical hardware and so operates as a normal machine.
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In order to make the basic information as accessible as possible, I’ll try to keep these descriptions at a high level and try to abstract many of the details. Memory and Memory Management Units (MMUs)